Fail safe built-in test equipment

ABSTRACT

Built-in test equipment (BITE) for an electronic system is implemented in a fail safe manner, with the test equipment itself not having failure modes which might inhibit detection of a system failure. The equipment insures detection of any single system failure and is in a &#39;&#39;&#39;&#39;No-Go&#39;&#39;&#39;&#39; condition if any tests in a test sequence are skipped.

United States Patent Feintuch et al.

FAIL SAFE BUILT-IN TEST EQUIPMENT Inventors: Martin W. Feintuch,Baramus; Allen S. Silver, Oakland, both of NJ.

Assignee: The Bendix Corportion, Teterboro,

Filed: June 29, 1972 Appl. No.: 267,285

[58] Field of Search... 340/248 A, 409; 235/92 CA,

235/92 CC, 92 EC US. Cl. 340/409, 340/248 A Int. Cl. G08b 21/00 Jan.22,1974 6/1972 Goldberg 340/409 X l/l973 Curran et al 340/248 A PrimaryExaminerDonald J. Yusko Assistant Examiner-Daniel Myer Attorney, Agent,or FirmAnthony F. Cuoco et al.

57 ABSTRACT 6 Claims, 1 Drawing Figure TIMING COMMAND I2 l8 2 2 I 24 k28 3 0 ;2 3 4 OUTPUT INPUT COUNTER MEMORY INTERFACE OBJECT I I T F FDEVICE SYSTEM l DEQITCQ 36 TEST COMPLETE A 6 J0 ADDRESS 2 as I v 22 6oDIGITAL COMPARATOR CLOCK 1 4O TIMING. MEMORY DEVICE T UNIT l AboREss 4s48 5 62 52 J s4 COUNTER EMP F 54 66 D NO so 1 FAIL SAFE BUILT-IN TESTEQUIPMENT BACKGROUND OF THE INVENTION 1. Field of the Invention Thisinvention relates to electronic systems including built-in testequipment. More particularly, the invention relates to systems of thetype described wherein the test equipment operates in a fail safemanner.

2. Description of the Prior Art 7 Aircraft control systems and the likerequire automa'tic self-testing capability to insure performance ofrequired functions. It is necessary that the equipment performing thetest does not itself possess failure modes that might inhibit thedetection of an actual system failure. Prior to the present invention,test equipment failures, have occurred which could cause a test to beskipped or a valid output to be provided, whether or not a systemfailure occurred.

SUMMARY OF THE INVENTION This invention comtemplates equipment of thetype described and including a timing device connected to a firstcounter which drives first and second memory units and connected througha gate to a second counter which drives a third memory unit. The firstmemory unit commands the timing device to provide pulses and activatesan output interface device. The output interface device applies testsignals to the system to be tested (object system) which responds bydriving an input interface device toprovide signals at discrete lev els.These signals are applied to a digital comparator and compared therebywith signals from the second memory unit. Any difference between thecompared signals forces, the output of the digital comparator to a truestate, and which output is applied through the gate to the secondcounter. When the pulses .from the timing device are at a predeterminedpulse width, the first counter will advance to the next count, but thesecond counter will so advance only if the output from the digitalcomparator is at a false state. In this fashion, the first countercounts the number of pulses provided by the timing device, whichcorresponds to the number of test steps, and the second counter countsthe pulses provided only if no difference is detected between commandedand actual object system response. 'When.

the first counter has counted a predetermined number of pulses the firstmemory unit provides a test complete signal and inhibits the timingdevice from providing additional pulses. When a predetermined number ofsuccessful test steps have been counted the third memory unit providesanother test complete" signal. A GO condition exists if both testcomplete signals are present and a NO GO condition exists if only one ofsaid signals is present.

One object of this invention is to provide built-in test equipment foran electrical system, and which test equipment is implemented in a failsafe manner.

Another object of this invention is to provide built-in test equipmentfor an electrical system, and wherein the test equipment itself does notpossess failure modes that might inhibit detection of an actual systemfailure.

Another object of this invention is to eliminate the condition wherefailure to the test equipment causes put regardless of test results.

' Another object of thisinvention is to provide equipment of the typedescribed which insures the detection of any single system failure.

Another object of this invention is to provide equipment of the typedescribed wherein a NO GO" condition exists if any tests in a testsequence are skipped.

The foregoing and other objects and advantages of the invention willappear more fully hereinafter from a consideration of the destaileddescription which follows, taken together with the accompanying drawingwherein one embodiment of the invention is illustrated by way ofexample. It is to be expressly understood, however, that the drawing isfor illustration purposes only and is not to be construed as definingthe limits of the invention.

DESCRIPTION OF THE DRAWING The single FIGURE in the drawing is a blockdiagram of apparatus constructed according to the invention.

DESCRIPTION OF THE INVENTION A memory unit 2 is connected through aconductor 4 to a timing device 6. Timing device 6 is connected through aconductor 8 and a conductor 10 to a counter 12 and through conductor 8and a conductor 14 to a gate 16. Counter 12 is connected through aconductor 18 to memory unit 2 and through conductor 18 and a conductor20 to a memory unit 22.

Memory unit 2 is connected through a conductor 24 to an output interfacedevice 26. Output interface device 26 is connected through a conductor28 to the object system i.e. the system to be tested, 30. Object system30 is connected through a conductor 32 to an input interface device 34.Input interface device 34 is connected through a conductor 36 to adigital comparator 38. Memory unit 22 is connected through a conductor40 to digital comparator 38.

Digital comparator 38 is connected through a conductor 42 to gate 16.Gate 16 is connected through a conductor 44 to a counter 46. Counter 46is connected through a conductor 48 to a memory unit 50. Memory unit 50is connected to a gate 52 through a conductor 54 and to a gate 56through conductor 54 and a conductor 58. Memory unit 2 is connected togate 56 through a conductor 60 and is connected to gate 52 throughconductor 60 and a conductor 62. A GO condition is provided at an outputconductor 64 connected to gate 52 and a NO-GO condition is provided atan output conductor 66 connected to gate 56.

The several components of the invention shown in the figure are standardcomponents well known in the art. The novelty of the invention residesin the arrangement of the components and not in the componentthemselves.

In this connection reference is made to the textbook Pulse Digital andSwitching Waveforms, by Millman and Taub, published by McGraw Hill BookCompany, 1965. Counters 12 and 46 may be of the type described at page660, in figure 18-1, output interface device 26 may be a digital toanalog converter of the type described at page 675, in figure 18-4 andinput interface device 34 may be an analog to digital converter alsodescribed at page 675 and shown in figure 18-4. Memory units 2, 22 and50 may be conventional read only memory (ROM) devices of the typedescribed in section 17-7, page 617 of the textbook, I ntegratcdElectronics Analog to Digital Circuits and Systems by Millman andHalkias, published by McGraw Hill Book Company in 1972. Digitalcomparator 38 may be an exclusive OR gate as is well known in the art.

Thus, timing device 6 provides pulses in accordance with a command frommemory unit 2. Counters l2 and 46 are arranged to provide a zero countwhen power is applied to the system and to advance one count for eachpulse received from timing device 6. Memory units, 2, 22, and 50 arearranged to provide logic signals at their output conductors as afunction of the address appearing at their input conductors.

Output interface device 26 is arranged for translating or conditioninglow power output signals from memory unit 2 to those signals necessaryto interrogate object system 30. Input interface 34 device translatesanalog signals and high power discrete signals to low power discretesignals. Digital comparator 38 compares pairs of input signals and setsits output line to a true state if, and only if, a discrepancy appearsin any of the pairs of input signals.

OPERATION OF THE INVENTION Memory unit 2 applies a timing command totiming device 6 and activates output interface device 26. Outputinterface device 26 applies test signals to object system 30 inaccordance with the inputs from memory unit 2.

Memory unit 22 applies signals to digital comparator 38. Object system30 responds to stimuli from output interface device 26 and forces theoutputs of various analog to digital counters in input device 34 todiscrete level signals. The discrete level signals from input interfacedevice 34 are applied to digital comparator 38 and compared thereby tothe signals from memory unit 22. Any discrepancy in the signals willforce the output of the digital comparator to the true state.

When the pulses from timing device 6 have attained a predetermined pulsewidth, a falling edge ofthe pulses is applied to counter 12 and to gate16. Counter 12 will thereupon advance to the next count. The outputfromdigital comparator 38 is applied through gate 16 which will providea signal to advance counter 46 to the next count only if the output fromthe digital comparator is at a false state.

Thus, counter 12 counts the number of pulses-provided by timing device6, and which number of pulses corresponds to the number of test steps ina test sequence. Counter 46 counts the number of pulses provided bytiming device 6 only if no difference is detected between the commandedand actual response of object system 30.

When counter 12 has counted a predetermined number of pulses, a testcomplete A signal is generated at the output of memory unit 2 and timingdevice 6 is commanded to emit a pulse of infinite width. In other words,the timing device is prevented from emitting more pulses.

Similarly counter 46 causes memory unit 50 to generate a test complete Bsignal when the specified number of successful test steps are counted. AGo condition is provided at the output of gate 64 if test complete A"and test complete B signals occur simultaneously. If only one testcomplete signal is present without the other, then a No Go indication isprovided'at the output of gate 66.

It will now be understood that a memory independent of that used togenerate input-signals to the system is used to generate the comparisonsignals. This insures the detection of any signal failure in thecircuitry located electrically between counter 12 and digital comparator38.

Since counter 12 is independent of counter 46, any failure that causeseither of the counters to skip tests will cause one of the two counterchannels to reach test complete status before the other thereby assuringa NO-GO situation.

A failure in digital comparator 38 is readily detectable by arrangingmemory unit 2 so that a known number of tests are not passed. If a testis erroneously passed, then the test complete B signal occurs prior totest complete A signal and a NO-GO condition results. If timing device 6fails, then either test complete A or test complete B signals occur anda NO- GO condition also results.

Although but a single embodiment of the invention has been illustratedand described in detail, it is to be expressly understood that theinvention is not limited thereto. Various changes may also be made inthe design and arrangement of the parts without departing from thespirit and scope of the invention as the same will now be understood bythose skilled in the art.

What is claimed is:

'1. Apparatus including a system and built-in equipment for testing thesystem, comprising:

a timing device for providing clock pulses;

a first counter connected to the timing'device and driven by the clockpulses therefrom;

first and second memory units connected to the first counter and driventhereby for providing first and second outputs;

a first interface device connected to the first memory unit and affectedby the first output for providing test signals;

a second interface device;

the system connected to the first and second interface devices andresponsive to the test signals from the first interface device fordriving the second interface device to provide an output at a discretelevel;

a comparator connected to the second memory unit and to the secondinterface device for comparing the second output and the output at adiscrete level, and for providing an output in one state when thecompared outputs differ and an output in another state when said outputscorrespond;

a second counter;

gating means connecting the second counter, to the timing device and tothe comparator;

the first counter driven by the clock pulses from the timing device tothe next succeeding count for counting the number of pulses from thetiming device which correspond to the number of test steps in a testsequence;

the second counter driven by the gating means to the next succeedingcount only if the output from the comparator is at the other state forcounting the number of successful test steps completed;

the first memory unit driven by the first counter to provide a firstsignal when a predetermined count is reached.

a third memory unit driven by the second counter to provide a secondsignal when the predetermined count is reached; and

means connected to the first and third memory units for providing a GOcondition when the first and second signals are both present; and aNO-GO condition when only one of said signals is present. 2. Apparatusincluding a system and built-in equipment for testing the system,comprising:

means for providing pulses;

means for counting said pulses and for providing a first signal when apredetermined number of pulses is counted, said count corresponding tothe number of steps in a test sequence;

means connected to the counting means and affected thereby when saidmeans is counting the pulses for applying test signals to the system;

means connected to the system and responsive thereto when the testsignals are applied for providing outputs at discrete levels;

means connected to the counting means for providing outputs inaccordance with the number of pulses counted thereby;

a comparator connected to the discrete output means and to the lastmentioned means for comparing the outputs therefrom and for providing afirst output when the compared outputs differ and a second output whensaid outputs correspond;

means connected to the pulse'providing means and to the comparator forproviding a second signal only if the comparator provides the secondoutput and the predetermined number of pulses are provided; and I meansconnected to the means for counting the pulses and to the last mentionedmeans for providing a 00" signal when both the first and second signalsare provided and a NO-GO signal when only one of said signals isprovided.

3. Apparatus as described by claim 2, wherein the means for countingsaid pulses and for providing a first signal when a predetermined numberof pulses is counted, said count corresponding to the number of steps ina test sequence includes:

a counter connected to the pulse providing means for counting the pulsestherefrom; and

a memory unit connected to the counter for providing the first signalwhen the predetermined number of pulses is counted.

4. Apparatus as described by claim 3, wherein:

the memory unit is connected to the pulse providing means forcontrolling the pulses provided thereby.

5. Apparatus as described by claim 4, wherein the means connected to thepulse providing means and to the comparator for providing a secondsignal only if the comparator provides the second output and thepredetermined number of pulses are provided includes:

a gate, connected to the pulse providing means and to the comparator forpassing the pulses from said means when the comparator provides thesecond output;

a counter connected to the gate for counting the pulses passed thereby;and

a memory unit for providing the second signal when the predeterminednumber of pulses are counted by the counter. I

6. Apparatus as described by claim 1, wherein:

the first memory unit is connected to the timing device for controllingthe pulses therefrom.

1. Apparatus including a system and built-in equipment for testing thesystem, comprising: a timing device for providing clock pulses; a firstcounter connected to the timing device and driven by the clock pulsestherefrom; first and second memory units connected to the first counterand driven thereby for providing first and second outputs; a firstinterface device connected to the first memory unit and affected by thefirst output for providing test signals; a second interface device; thesystem connected to the first and second interface devices andresponsive to the test signals from the first interface device fordriving the second interface device to provide an output at a discretelevel; a comparator connected to the second memory unit and to thesecond interface device for comparing the second output and the outputat a discrete level, and for providing an output in one state when thecompared outputs differ and an output in another state when said outputscorrespond; a second counter; gating means connecting the secondcounter, to the timing device and to the comparator; the first counterdriven by the clock pulses from the timing device to the next succeedingcount for counting the number of pulses from the timing device whichcorrespond to the number of test steps in a test sequence; the secondcounter driven by the gating means to the next succeeding count only ifthe output from the comparator is at the other state for counting thenumber of successful test steps completed; the first memory unit drivenby the first counter to provide a first signal when a predeterminedcount is reached. a third memory unit driven by the second counter toprovide a second signal when the predetermined count is reached; andmeans connected to the first and third memory units for providing a''''GO'''' condition when the first and second signals are both present;and a ''''NO-GO'''' condition when only one of said signals is present.2. Apparatus including a system and built-in equipment for testing thesystem, comprising: means for providing pulses; means for counting saidpulses and for providing a first signal when a predetermined number ofpulses is counted, said count corresponding to the number of steps in atest sequence; means connected to the counting means and affectedthereby when said means is counting the pulses for applying test signalsto the system; means connected to the system and responsive thereto whenthe test signals are applied for providing outputs at discrete levels;means connected to the counting means for providing outputs inaccordance with the number of pulses counted thereby; a comparatorconnected to the discrete output means and to the last mentioned meansfor comparing the outputs therefrom and for providing a first outputwhen the compared outputs differ and a second output when said outputscorrespond; means connected to the pulse providing means and to thecomparator for providing a second signal only if the comparator providesthe second output and the predetermined number of pulses are provided;and means connected to the means for counting the pulses and to the lastmentioned means for providing a ''''GO'''' signal when both the firstand second signals are provided and a ''''NO-GO'''' signal when only oneof said signals is provided.
 3. Apparatus as described by claim 2,wherein the means for counting said pulses and for providing a firstsignal when a predetermined number of pulses is counted, said countcorresponding to the number of steps in a test sequence includes: acounter connected to the pulse providing means for counting the pulsestherefrom; and a memory unit connected to the counter for providing thefirst signal when the predetermined number of pulses is counted. 4.Apparatus as described by claim 3, wherein: the memory unit is connectedto the pulse providing means for controlling the pulses providedthereby.
 5. Apparatus as described by claim 4, wherein the meansconnected to the pulse providing means and to the comparator forproviding a second signal only if the comparator provides the secondoutput and the predetermined number of pulses are provided includes: agate, connected to the pulse providing means and to the comparator forpassing the pulses from said means when the comparator provides thesecond output; a counter connected to the gate for counting the pulsespassed thereby; and a memory unit for providing the second signal whenthe predetermined number of pulses are counted by the counter. 6.Apparatus as described by claim 1, wherein: the first memory unit isconnected to the timing device for controlling the pulses therefrom.